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Overview:
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   The Neotoma 1 processor is a small footprint load-store architecutre
   0-operand (zero-address) stack machine where all ALU operations take
   place using only the top one or two data stack values.

   The MCU executes microcode instructions which are expanded from a more
   more traditional set of assembly language opcoces using the assembler.

   Build prameters allow for the MCU to be sized appropriate to its use.
   The MCU data width is identical for the Data Stack, Call Stack, ALU, 
   Data Memory, and Program Memory.

   The MCU is Harvard architecture where the Program RAM and Data RAM
   are separate and independent with paramaterized sizes.
   The minimum Program Memory data width is 8-bits to encode the microcode 
   instruction set.

   The Call Stack is located at the top of the Data Memory and allows for
   local subroutine variables.

   The Data Stack has independent RAM with a paramaterized size.

   The assembler generates .hex files for both the program memory and
   for the initial main data memory. Both the program memory and the
   main data memory can independetly be programmed either with initial
   values at MCU build time or interactively at any time the MCU is 
   held in reset using the RAM Arbiter ports to access the memories.

   The MCU has GPIO input and output via external memory MMAP load/store.
   The MCU has UART input and output via external memory MMAP load/store.

   The MCU has a single and double word product multiply and has double
   word arithmetic shift instructions to help support fixed point arithmetic.

   RTL verification is directed test bench (DTB) self-checking simulation.
   The assembler verification is set of suite self-checking tests.

   Synthesizable demo for the Digilent Basys3 Artix 7 FPGA prototyping board.
   The demo is a 16-bit counter displaying as four hex nibbles on the Basys3
   seven sgement display. A button press will run a bubble sort on the four
   hex nibbles reordering them from hight to low.
   The demo include synthesis build scripts and debugging simulation scripts.

   Xilinx Vivado is used for simulation, testbench, and synthesis.

   The Neotoma 1 processor is released under the LGPL.